As data transfer speeds for network communications increase, timing among network system components becomes increasingly critical. To address this issue, highly accurate timing sources have been established which can provide common timing information to devices which in turn can distribute such common timing information to network system devices. Unfortunately, the direct distribution of such a highly accurate timing signal to the many elements which can be found in a common data communications network comes only at a high cost in terms of capital investment and space, power and cooling requirements. Further, due to the high data transfer speeds, synchronization between network elements must still be maintained.
For instance, a primary reference source or PRS, such as a highly accurate stratum 1 clock, is distributed through a wide-area/public network. Stratum 2 clocks are synchronized to the stratum 1 clock signal and serve to distribute the original timing signal to multiple subsequent devices. In the prior art, the output of such stratum 2 clocks are received by stratum 3 clocks which are installed in conjunction with various distributed devices within a data communications network. These stratum 2 clock output signals are also referred to as Building Integrated Timing Signal (BITS) clocks. The stratum 3 clock generates a timing signal, based upon the original stratum 1 clock signal, which is used locally with respect to the stratum 3 clock.
Several problems become apparent with the utilization of BITS clocks at each network device having a stratum 3 clock. Stratum 2 clocks are expensive, physical installation requirements can add to the overall cost of network installation, and the physical infrastructure required to distribute the BITS timing signal output to various stratum 3 clocks is potentially expensive and complex. Such high accuracy clocks also represent potentially expensive repair candidates. Thus, it would be beneficial to distribute timing signals within a data communications network as inputs to distributed stratum 3 clocks while minimizing the number of stratum 2 clocks and reliance upon respective BITS clock lines, and while enabling enhanced flexibility in terms of selecting timing signal sources and the distribution of such signals.
A further drawback to the usage of plural stratum 2 clocks in a data communications network lies in the outcome of a failure of one of the stratum 2 clocks. If such a failure occurs, the respective device or devices in the network are left without a centralized timing signal, and are left to rely upon a locally-generated timing signal source, which is free running with respect to the remainder of the network, or to a timing signal recovered from an incoming data stream.
Prior art data communications network devices such as switches have heretofore failed to provide system developers with adequate flexibility in terms of choosing from among plural timing signals. Typically, such a switch can employ an externally applied timing signal such as a BITS clock, a recovered clock signal derived from an incoming data stream, or a locally generated clock signal such as from a local oscillator. Flexibility in choosing from among these sources is very desirable to assure timing synchronization to a single clock and to enable cost savings.
Many prior art data networks also fail to provide redundant timing sources such that flexibility in choosing from among plural timing sources is enabled, in addition to the aforementioned flexibility in choosing the source of the common timing signal.
The prior art also suffers from deficiencies with specific reference to data communications network elements such as switches. Prior art switches have commonly employed asynchronous elements within the switch, thus requiring a significant degree of buffering, which is both expensive and tends to increase latency through the switch. Further, such asynchronous systems tend to have higher data loss characteristics, further reducing transfer rates through the necessity of retransmission.
Additionally, prior art switches have failed to provide "seamless" redundancy in internal timing reference sources such that no data is lost when it becomes necessary to switchover between redundant internal timing sources.